bare_metal
bare metal is an FPGA development board - the ideal platform to get started with FPGAs and HDL of one or another sort. all open source.
bare_metal, the opensource FPGA development board:
- five user buttons: OK, left, right, up, down
- large 16x8 SPI-addressable RGB LEDs display
- extensible through a PMOD interface
- comes with a battery for many hours of runtime
- extensive power management, monitoring and battery protection in HW
- allows for CPU-less designs or soft-core CPUs
- get into FPGAs with the yosys and nextpnr all open source toolchains
- program in python/amarant, verilog, spade or others
- comes with a stand
- three bright white LEDs as simple debug or flashlight
- usable as name tag, comes with a lace
- comes with a bootloader as 1st of four bitstreams
- can host up to 3 user bitstreams
- 16MBytes flash in total (1 bitstream takes < 128kBytes)
- 8MBytes RAM in total
- transputer research platform, as 3 user bitstreams can "boot" each other, see
bootloaderbelow - hacky but feasible: more that 3 user bitstreams (hundreds)
the FPGA
it's a Lattice iCE40 UP5K in a SG48 package
- fully supported by yosys and nextpnr
- 5000+ LUTs
- 8 DSP blocks (MULT16 with ACC32)
- 1024kBits SPRAM in 4 blocks
- 120kBits EBR memory in 30 blocks
- 2 hard I2C blocks
- 2 hard SPI blocks
sources, schematics, documentation
all hardware, software and firmware is documented on the main project page
buy
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